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panxiang 68a9b7dceb 可以编译通过的工程
2026-02-05 18:42:08 +08:00
modules/LVDS
可以编译通过的工程
2026-02-05 18:42:08 +08:00
top_src
可以编译通过的工程
2026-02-05 18:42:08 +08:00
.gitignore
初始的工程参考
2026-02-02 17:58:25 +08:00
project_gen.tcl
可以编译通过的工程
2026-02-05 18:42:08 +08:00
README.md
Initial commit
2026-02-02 16:52:16 +08:00
Sourceprj.bat
初始的工程参考
2026-02-02 17:58:25 +08:00

README.md

LVDS1M

LVDS 1 对 多 输出

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Description
LVDS1M
Readme 46 KiB
Languages
Tcl 69.4%
Verilog 27.9%
Batchfile 2.7%