diff --git a/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci b/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci new file mode 100644 index 0000000..2bb676d --- /dev/null +++ b/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci @@ -0,0 +1,209 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "selectio_wiz_in", + "component_reference": "xilinx.com:ip:selectio_wiz:5.1", + "ip_revision": "18", + "gen_directory": "../../../../vivado_prj.gen/sources_1/ip/selectio_wiz_in", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "selectio_wiz_in", "resolve_type": "user", "usage": "all" } ], + "NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "USE_TEMPLATE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "BUS_DIR": [ { "value": "INPUTS", "resolve_type": "user", "usage": "all" } ], + "BUS_SIG_TYPE": [ { "value": "DIFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "BUS_IO_STD": [ { "value": "LVDS_25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "USE_PHASE_DETECTOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SELIO_ACTIVE_EDGE": [ { "value": "SDR", "resolve_type": "user", "usage": "all" } ], + "USE_SERIALIZATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SERIALIZATION_FACTOR": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ENABLE_BITSLIP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_TRAIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "TRAIN_CONSTANT": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "SYSTEM_DATA_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "user", "usage": "all" } ], + "SELIO_INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "user", "usage": "all" } ], + "BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "SELIO_BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "BUS_IN_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SELIO_BUS_IN_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUS_TAP_RESET": [ { "value": "NOT_APP", "resolve_type": "user", "usage": "all" } ], + "BUS_TAP_WRAP": [ { "value": "NOT_APP", "resolve_type": "user", "usage": "all" } ], + "BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "SELIO_BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "BUS_OUT_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SELIO_BUS_OUT_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_SIG_TYPE": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "SELIO_CLK_SIG_TYPE": [ { "value": "DIFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_IO_STD": [ { "value": "LVCMOS18", "resolve_type": "user", "usage": "all" } ], + "SELIO_CLK_IO_STD": [ { "value": "LVDS_25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_BUF": [ { "value": "BUFIO2", "resolve_type": "user", "usage": "all" } ], + "SELIO_CLK_BUF": [ { "value": "BUFIO", "resolve_type": "user", "usage": "all" } ], + "ACTIVE_EDGE": [ { "value": "RISING", "resolve_type": "user", "usage": "all" } ], + "DDR_ALIGNMENT": [ { "value": "C0", "resolve_type": "user", "usage": "all" } ], + "SELIO_DDR_ALIGNMENT": [ { "value": "SAME_EDGE_PIPELINED", "resolve_type": "user", "usage": "all" } ], + "SELIO_ODDR_ALIGNMENT": [ { "value": "SAME_EDGE", "resolve_type": "user", "usage": "all" } ], + "CLK_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "CLK_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_FWD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_FWD_SER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "user", "usage": "all" } ], + "SELIO_IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "user", "usage": "all" } ], + "CLK_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CONFIG_CLK_FWD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_FWD_SIG_TYPE": [ { "value": "DIFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_FWD_IO_STD": [ { "value": "LVDS_25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "DDR_CLK_BUF": [ { "value": "BUFR", "resolve_type": "user", "usage": "all" } ], + "INCLUDE_IDELAYCTRL": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "INCLUDE_IDELAYCTRL_BUFG": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "IDELAY_HIGH_PERF_MODE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "c_component_name": [ { "value": "selectio_wiz_in", "resolve_type": "generated", "usage": "all" } ], + "C_INCLUDE_IDELAYCTRL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INCLUDE_IDELAYCTRL_BUFG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DEVICE_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ], + "C_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_DIR": [ { "value": "INPUTS", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_SIG_TYPE": [ { "value": "DIFF", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_IO_STD": [ { "value": "LVDS_25", "resolve_type": "generated", "usage": "all" } ], + "C_USE_SERIALIZATION": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_SERIALIZATION_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_PHASE_DETECTOR": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_ENABLE_BITSLIP": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_ENABLE_TRAIN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_TRAIN_CONSTANT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SYSTEM_DATA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_IN_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SELIO_BUS_IN_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BUS_TAP_RESET": [ { "value": "FROM_ZERO", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_TAP_WRAP": [ { "value": "STAY_AT_LIMIT", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_OUT_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SELIO_BUS_OUT_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLK_SIG_TYPE": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_IO_STD": [ { "value": "LVCMOS18", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_CLK_SIG_TYPE": [ { "value": "DIFF", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_CLK_IO_STD": [ { "value": "LVDS_25", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_BUF": [ { "value": "BUFIO2", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_CLK_BUF": [ { "value": "BUFIO", "resolve_type": "generated", "usage": "all" } ], + "C_ACTIVE_EDGE": [ { "value": "RISING", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_ACTIVE_EDGE": [ { "value": "SDR", "resolve_type": "generated", "usage": "all" } ], + "C_INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "generated", "usage": "all" } ], + "C_DDR_ALIGNMENT": [ { "value": "C0", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_DDR_ALIGNMENT": [ { "value": "SAME_EDGE_PIPELINED", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_ODDR_ALIGNMENT": [ { "value": "SAME_EDGE", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLK_TAP_reset": [ { "value": "FROM_ZERO", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_TAP_wrap": [ { "value": "STAY_AT_LIMIT", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_FWD": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_USE_TEMPLATE": [ { "value": "Custom", "resolve_type": "generated", "usage": "all" } ], + "C_DATA_RATE_STRING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DEVICE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_EN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_CLK_FWD_SIG_TYPE": [ { "value": "DIFF", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_FWD_IO_STD": [ { "value": "LVDS_25", "resolve_type": "generated", "usage": "all" } ], + "C_CONFIG_CLK_FWD": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], + "C_DDR_CLK_BUF": [ { "value": "BUFR", "resolve_type": "generated", "usage": "all" } ], + "C_IDELAY_HIGH_PERF_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "18" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../vivado_prj.gen/sources_1/ip/selectio_wiz_in" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2024.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "data_in_from_pins_p": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "data_in_from_pins_n": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "clk_in_p": [ { "direction": "in", "driver_value": "0" } ], + "clk_in_n": [ { "direction": "in", "driver_value": "0" } ], + "io_reset": [ { "direction": "in", "driver_value": "0" } ], + "clk_out": [ { "direction": "out" } ], + "data_in_to_device": [ { "direction": "out", "size_left": "3", "size_right": "0" } ] + }, + "interfaces": { + "io_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "io_reset" } ] + } + }, + "diff_clk_in": { + "vlnv": "xilinx.com:interface:diff_clock:1.0", + "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0", + "mode": "slave", + "parameters": { + "CAN_DEBUG": [ { "value": "false", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_N": [ { "physical_name": "clk_in_n" } ], + "CLK_P": [ { "physical_name": "clk_in_p" } ] + } + }, + "data_in_to_device": { + "vlnv": "xilinx.com:signal:data:1.0", + "abstraction_type": "xilinx.com:signal:data_rtl:1.0", + "mode": "master", + "parameters": { + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "DATA": [ { "physical_name": "data_in_to_device" } ] + } + }, + "clk_out": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "clk_out" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci b/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci new file mode 100644 index 0000000..e9a092d --- /dev/null +++ b/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci @@ -0,0 +1,222 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "selectio_wiz_out", + "component_reference": "xilinx.com:ip:selectio_wiz:5.1", + "ip_revision": "18", + "gen_directory": "../../../../vivado_prj.gen/sources_1/ip/selectio_wiz_out", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "selectio_wiz_out", "resolve_type": "user", "usage": "all" } ], + "NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "USE_TEMPLATE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "BUS_DIR": [ { "value": "OUTPUTS", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "BUS_SIG_TYPE": [ { "value": "DIFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "BUS_IO_STD": [ { "value": "LVDS_25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "USE_PHASE_DETECTOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SELIO_ACTIVE_EDGE": [ { "value": "SDR", "resolve_type": "user", "usage": "all" } ], + "USE_SERIALIZATION": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SERIALIZATION_FACTOR": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ENABLE_BITSLIP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_TRAIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "TRAIN_CONSTANT": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "SYSTEM_DATA_WIDTH": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "user", "usage": "all" } ], + "SELIO_INTERFACE_TYPE": [ { "value": "NETWORKING", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "SELIO_BUS_IN_DELAY": [ { "value": "NONE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "BUS_IN_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SELIO_BUS_IN_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUS_TAP_RESET": [ { "value": "NOT_APP", "resolve_type": "user", "usage": "all" } ], + "BUS_TAP_WRAP": [ { "value": "NOT_APP", "resolve_type": "user", "usage": "all" } ], + "BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "SELIO_BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "BUS_OUT_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SELIO_BUS_OUT_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_SIG_TYPE": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "SELIO_CLK_SIG_TYPE": [ { "value": "DIFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_IO_STD": [ { "value": "LVCMOS18", "resolve_type": "user", "usage": "all" } ], + "SELIO_CLK_IO_STD": [ { "value": "LVDS_25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_BUF": [ { "value": "BUFIO2", "resolve_type": "user", "usage": "all" } ], + "SELIO_CLK_BUF": [ { "value": "MMCM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ACTIVE_EDGE": [ { "value": "RISING", "resolve_type": "user", "usage": "all" } ], + "DDR_ALIGNMENT": [ { "value": "C0", "resolve_type": "user", "usage": "all" } ], + "SELIO_DDR_ALIGNMENT": [ { "value": "SAME_EDGE_PIPELINED", "resolve_type": "user", "usage": "all" } ], + "SELIO_ODDR_ALIGNMENT": [ { "value": "SAME_EDGE", "resolve_type": "user", "usage": "all" } ], + "CLK_DELAY": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ], + "CLK_TAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_FWD": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_FWD_SER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "user", "usage": "all" } ], + "SELIO_IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "user", "usage": "all" } ], + "CLK_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CONFIG_CLK_FWD": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_FWD_SIG_TYPE": [ { "value": "DIFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_FWD_IO_STD": [ { "value": "LVDS_25", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "DDR_CLK_BUF": [ { "value": "BUFR", "resolve_type": "user", "usage": "all" } ], + "INCLUDE_IDELAYCTRL": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "INCLUDE_IDELAYCTRL_BUFG": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "IDELAY_HIGH_PERF_MODE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "c_component_name": [ { "value": "selectio_wiz_out", "resolve_type": "generated", "usage": "all" } ], + "C_INCLUDE_IDELAYCTRL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_INCLUDE_IDELAYCTRL_BUFG": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DEVICE_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ], + "C_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_DIR": [ { "value": "OUTPUTS", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_SIG_TYPE": [ { "value": "DIFF", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_IO_STD": [ { "value": "LVDS_25", "resolve_type": "generated", "usage": "all" } ], + "C_USE_SERIALIZATION": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_SERIALIZATION_FACTOR": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USE_PHASE_DETECTOR": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_ENABLE_BITSLIP": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_ENABLE_TRAIN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_TRAIN_CONSTANT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SYSTEM_DATA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_BUS_IN_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_IN_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SELIO_BUS_IN_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BUS_TAP_RESET": [ { "value": "FROM_ZERO", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_TAP_WRAP": [ { "value": "STAY_AT_LIMIT", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_BUS_OUT_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_BUS_OUT_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SELIO_BUS_OUT_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLK_SIG_TYPE": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_IO_STD": [ { "value": "LVCMOS18", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_CLK_SIG_TYPE": [ { "value": "DIFF", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_CLK_IO_STD": [ { "value": "LVDS_25", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_BUF": [ { "value": "BUFIO2", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_CLK_BUF": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_ACTIVE_EDGE": [ { "value": "RISING", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_ACTIVE_EDGE": [ { "value": "SDR", "resolve_type": "generated", "usage": "all" } ], + "C_INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_INTERFACE_TYPE": [ { "value": "NETWORKING", "resolve_type": "generated", "usage": "all" } ], + "C_DDR_ALIGNMENT": [ { "value": "C0", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_DDR_ALIGNMENT": [ { "value": "SAME_EDGE_PIPELINED", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_ODDR_ALIGNMENT": [ { "value": "SAME_EDGE", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_DELAY": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_TAP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLK_TAP_reset": [ { "value": "FROM_ZERO", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_TAP_wrap": [ { "value": "STAY_AT_LIMIT", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_FWD": [ { "value": "true", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_USE_TEMPLATE": [ { "value": "Custom", "resolve_type": "generated", "usage": "all" } ], + "C_DATA_RATE_STRING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_DEVICE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "generated", "usage": "all" } ], + "C_SELIO_IDDR_RST_TYPE": [ { "value": "ASYNC", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_EN": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "C_CLK_FWD_SIG_TYPE": [ { "value": "DIFF", "resolve_type": "generated", "usage": "all" } ], + "C_CLK_FWD_IO_STD": [ { "value": "LVDS_25", "resolve_type": "generated", "usage": "all" } ], + "C_CONFIG_CLK_FWD": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ], + "C_DDR_CLK_BUF": [ { "value": "BUFR", "resolve_type": "generated", "usage": "all" } ], + "C_IDELAY_HIGH_PERF_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z020" } ], + "PACKAGE": [ { "value": "clg400" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "18" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../vivado_prj.gen/sources_1/ip/selectio_wiz_out" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2024.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "data_out_to_pins_p": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "data_out_to_pins_n": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "clk_in": [ { "direction": "in", "driver_value": "0" } ], + "data_out_from_device": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "clk_reset": [ { "direction": "in", "driver_value": "0" } ], + "io_reset": [ { "direction": "in", "driver_value": "0" } ], + "clk_to_pins_p": [ { "direction": "out" } ], + "clk_to_pins_n": [ { "direction": "out" } ] + }, + "interfaces": { + "io_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "io_reset" } ] + } + }, + "clk_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "clk_reset" } ] + } + }, + "Clk_in": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "clk_in" } ] + } + }, + "data_out_from_device": { + "vlnv": "xilinx.com:signal:data:1.0", + "abstraction_type": "xilinx.com:signal:data_rtl:1.0", + "mode": "slave", + "parameters": { + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "DATA": [ { "physical_name": "data_out_from_device" } ] + } + }, + "diff_clk_to_pins": { + "vlnv": "xilinx.com:interface:diff_clock:1.0", + "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0", + "mode": "master", + "parameters": { + "CAN_DEBUG": [ { "value": "false", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_N": [ { "physical_name": "clk_to_pins_n" } ], + "CLK_P": [ { "physical_name": "clk_to_pins_p" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/modules/LVDS/rtl/lvds_1to3bypass.v b/modules/LVDS/rtl/lvds_1to3bypass.v new file mode 100644 index 0000000..aaacf86 --- /dev/null +++ b/modules/LVDS/rtl/lvds_1to3bypass.v @@ -0,0 +1,109 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2026/02/02 18:13:16 +// Design Name: +// Module Name: top_module +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module lvds_1to3bypass( + + input wire CLK_p,CLK_n, + input wire [3:0] DATA_p,DATA_n, + // ------------------------------------------- + output wire CLK0_p,CLK0_n, + output wire [3:0] DATA0_p,DATA0_n, + // ------------------------------------------- + output wire CLK1_p,CLK1_n, + output wire [3:0] DATA1_p,DATA1_n, + // ------------------------------------------- + output wire CLK2_p,CLK2_n, + output wire [3:0] DATA2_p,DATA2_n, + // input sys_clk_50, + input io_reset + + ); + + + wire [3:0] data_in_to_device; + wire clk_out; + + selectio_wiz_in lvds_in1( + // From the system into the device + .data_in_from_pins_p(DATA_p), // + .data_in_from_pins_n(DATA_n), // + + .data_in_to_device(data_in_to_device), + + .clk_in_p(CLK_p), // // Differential clock from IOB + .clk_in_n(CLK_n), // + + .clk_out(clk_out),// + .io_reset(io_reset) + + ); + + + selectio_wiz_out lvdsout0 ( + // From the device out to the system + .data_out_from_device(data_in_to_device), + + .data_out_to_pins_p(DATA0_p), + .data_out_to_pins_n(DATA0_n), + .clk_to_pins_p(CLK0_p), + .clk_to_pins_n(CLK0_n), + + .clk_in(clk_out), // Fast clock input from PLL/MMCM + .clk_reset(io_reset), + .io_reset(io_reset) + ); + + selectio_wiz_out lvdsout1 ( + + // From the device out to the system + .data_out_from_device(data_in_to_device), + + .data_out_to_pins_p(DATA1_p), + .data_out_to_pins_n(DATA1_n), + .clk_to_pins_p(CLK1_p), + .clk_to_pins_n(CLK1_n), + + .clk_in(clk_out), // Fast clock input from PLL/MMCM + .clk_reset(io_reset), + .io_reset(io_reset) + ); + + selectio_wiz_out lvdsout2 ( + + // From the device out to the system + .data_out_from_device(data_in_to_device), + + .data_out_to_pins_p(DATA2_p), + .data_out_to_pins_n(DATA2_n), + .clk_to_pins_p(CLK2_p), + .clk_to_pins_n(CLK2_n), + + .clk_in(clk_out), // Fast clock input from PLL/MMCM + .clk_reset(io_reset), + .io_reset(io_reset) + ); + + +endmodule + + + diff --git a/project_gen.tcl b/project_gen.tcl index d86925f..5755d0c 100644 --- a/project_gen.tcl +++ b/project_gen.tcl @@ -3,7 +3,7 @@ # # project_gen.tcl: Tcl script for re-creating project 'vivado_prj' # -# Generated by Vivado on Mon Feb 02 17:52:29 +0800 2026 +# Generated by Vivado on Thu Feb 05 18:31:49 +0800 2026 # IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -23,12 +23,17 @@ # 2. The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # -# +# "D:/vivadoworkspace/LVDS1M/vivado_prj/vivado_prj.srcs/utils_1/imports/synth_1/top_module.dcp" # # 3. The following remote source files that were added to the original project:- # -# "D:/vivadoworkspace/LVDS1M/modules/LVDS/rtl/lvds_1to3_copy_reg.v" +# "D:/vivadoworkspace/LVDS1M/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci" +# "D:/vivadoworkspace/LVDS1M/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci" +# "D:/vivadoworkspace/LVDS1M/modules/LVDS/rtl/lvds_1to3bypass.v" +# "D:/vivadoworkspace/LVDS1M/top_src/rtl/top_module.v" # "D:/vivadoworkspace/LVDS1M/modules/LVDS/sim/testbench/tb_lvds_1to3_copy_reg.v" +# "D:/vivadoworkspace/LVDS1M/modules/LVDS/rtl/lvds_1to3_copy_reg.v" +# "D:/vivadoworkspace/LVDS1M/top_src/constrains/top_module.xdc" # #***************************************************************************************** @@ -36,8 +41,23 @@ proc checkRequiredFiles { origin_dir} { set status true set files [list \ - "[file normalize "$origin_dir/modules/LVDS/rtl/lvds_1to3_copy_reg.v"]"\ + "[file normalize "$origin_dir/vivado_prj/vivado_prj.srcs/utils_1/imports/synth_1/top_module.dcp"]"\ + ] + foreach ifile $files { + if { ![file isfile $ifile] } { + puts " Could not find local file $ifile " + set status false + } + } + + set files [list \ + "[file normalize "$origin_dir/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci"]"\ + "[file normalize "$origin_dir/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci"]"\ + "[file normalize "$origin_dir/modules/LVDS/rtl/lvds_1to3bypass.v"]"\ + "[file normalize "$origin_dir/top_src/rtl/top_module.v"]"\ "[file normalize "$origin_dir/modules/LVDS/sim/testbench/tb_lvds_1to3_copy_reg.v"]"\ + "[file normalize "$origin_dir/modules/LVDS/rtl/lvds_1to3_copy_reg.v"]"\ + "[file normalize "$origin_dir/top_src/constrains/top_module.xdc"]"\ ] foreach ifile $files { if { ![file isfile $ifile] } { @@ -127,7 +147,7 @@ if { $validate_required } { } # Create project -create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1 +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-2 # Set the directory path for the new project set proj_dir [get_property directory [current_project]] @@ -143,18 +163,18 @@ set_property -name "enable_vhdl_2008" -value "1" -objects $obj set_property -name "ip_cache_permissions" -value "read write" -objects $obj set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj -set_property -name "part" -value "xc7z020clg400-1" -objects $obj +set_property -name "part" -value "xc7z020clg400-2" -objects $obj set_property -name "revised_directory_structure" -value "1" -objects $obj set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "sim_compile_state" -value "1" -objects $obj set_property -name "use_inline_hdl_ip" -value "1" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "3" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "3" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "3" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "3" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "3" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj set_property -name "webtalk.xsim_launch_sim" -value "1" -objects $obj # Create 'sources_1' fileset (if not found) @@ -165,12 +185,34 @@ if {[string equal [get_filesets -quiet sources_1] ""]} { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ + [file normalize "${origin_dir}/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci"] \ + [file normalize "${origin_dir}/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci"] \ + [file normalize "${origin_dir}/modules/LVDS/rtl/lvds_1to3bypass.v"] \ + [file normalize "${origin_dir}/top_src/rtl/top_module.v"] \ + [file normalize "${origin_dir}/modules/LVDS/sim/testbench/tb_lvds_1to3_copy_reg.v"] \ [file normalize "${origin_dir}/modules/LVDS/rtl/lvds_1to3_copy_reg.v"] \ ] add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files -# None +set file "$origin_dir/modules/LVDS/ip/selectio_wiz_out/selectio_wiz_out.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/modules/LVDS/ip/selectio_wiz_in/selectio_wiz_in.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + # Set 'sources_1' fileset file properties for local files # None @@ -178,8 +220,7 @@ add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset properties set obj [get_filesets sources_1] set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj -set_property -name "top" -value "lvds_1to3_copy_reg" -objects $obj -set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top" -value "top_module" -objects $obj # Create 'constrs_1' fileset (if not found) if {[string equal [get_filesets -quiet constrs_1] ""]} { @@ -189,11 +230,17 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} { # Set 'constrs_1' fileset object set obj [get_filesets constrs_1] -# Empty (no sources present) +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/top_src/constrains/top_module.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/top_src/constrains/top_module.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj # Set 'constrs_1' fileset properties set obj [get_filesets constrs_1] -set_property -name "target_part" -value "xc7z020clg400-1" -objects $obj +set_property -name "target_part" -value "xc7z020clg400-2" -objects $obj # Create 'sim_1' fileset (if not found) if {[string equal [get_filesets -quiet sim_1] ""]} { @@ -202,26 +249,34 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] -set files [list \ - [file normalize "${origin_dir}/modules/LVDS/sim/testbench/tb_lvds_1to3_copy_reg.v"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'sim_1' fileset file properties for remote files -# None - -# Set 'sim_1' fileset file properties for local files -# None +# Empty (no sources present) # Set 'sim_1' fileset properties set obj [get_filesets sim_1] set_property -name "sim_wrapper_top" -value "1" -objects $obj set_property -name "top" -value "tb_lvds_1to3_copy_reg" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj # Set 'utils_1' fileset object set obj [get_filesets utils_1] -# Empty (no sources present) +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/vivado_prj/vivado_prj.srcs/utils_1/imports/synth_1/top_module.dcp" ]\ +] +set imported_files "" +foreach f $files { + lappend imported_files [import_files -fileset utils_1 $f] +} + +# Set 'utils_1' fileset file properties for remote files +# None + +# Set 'utils_1' fileset file properties for local files +set file "synth_1/top_module.dcp" +set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]] +set_property -name "netlist_only" -value "0" -objects $file_obj + # Set 'utils_1' fileset properties set obj [get_filesets utils_1] @@ -234,7 +289,7 @@ catch { # Create 'synth_1' run (if not found) if {[string equal [get_runs -quiet synth_1] ""]} { - create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 + create_run -name synth_1 -part xc7z020clg400-2 -flow {Vivado Synthesis 2024} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 } else { set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] set_property flow "Vivado Synthesis 2024" [get_runs synth_1] @@ -252,236 +307,241 @@ if { $obj != "" } { } set obj [get_runs synth_1] -set_property -name "part" -value "xc7z020clg400-1" -objects $obj +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "part" -value "xc7z020clg400-2" -objects $obj +set_property -name "incremental_checkpoint" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/synth_1/top_module.dcp" -objects $obj set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj # set the current synth run current_run -synthesis [get_runs synth_1] -# Create 'impl_1' run (if not found) -if {[string equal [get_runs -quiet impl_1] ""]} { - create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +# Create 'impl_1_copy_1' run (if not found) +if {[string equal [get_runs -quiet impl_1_copy_1] ""]} { + create_run -name impl_1_copy_1 -part xc7z020clg400-2 -flow {Vivado Implementation 2024} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 } else { - set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] - set_property flow "Vivado Implementation 2024" [get_runs impl_1] + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1_copy_1] + set_property flow "Vivado Implementation 2024" [get_runs impl_1_copy_1] } -set obj [get_runs impl_1] +set obj [get_runs impl_1_copy_1] set_property set_report_strategy_name 1 $obj set_property report_strategy {Vivado Implementation Default Reports} $obj set_property set_report_strategy_name 0 $obj -# Create 'impl_1_init_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +# Create 'impl_1_copy_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_init_report_timing_summary_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_opt_report_drc_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { - create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +# Create 'impl_1_copy_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_copy_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_drc_0] if { $obj != "" } { } -# Create 'impl_1_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +# Create 'impl_1_copy_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_opt_report_timing_summary_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +# Create 'impl_1_copy_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_power_opt_report_timing_summary_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_place_report_io_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { - create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +# Create 'impl_1_copy_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_io_0] if { $obj != "" } { } -# Create 'impl_1_place_report_utilization_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { - create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +# Create 'impl_1_copy_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_utilization_0] if { $obj != "" } { } -# Create 'impl_1_place_report_control_sets_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { - create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +# Create 'impl_1_copy_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_control_sets_0] if { $obj != "" } { set_property -name "options.verbose" -value "1" -objects $obj } -# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { - create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +# Create 'impl_1_copy_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj } -# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { - create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +# Create 'impl_1_copy_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_incremental_reuse_1] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj } -# Create 'impl_1_place_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +# Create 'impl_1_copy_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_place_report_timing_summary_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +# Create 'impl_1_copy_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_place_power_opt_report_timing_summary_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +# Create 'impl_1_copy_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_phys_opt_report_timing_summary_0] if { $obj != "" } { set_property -name "is_enabled" -value "0" -objects $obj set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_route_report_drc_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { - create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_drc_0] if { $obj != "" } { } -# Create 'impl_1_route_report_methodology_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { - create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_methodology_0] if { $obj != "" } { } -# Create 'impl_1_route_report_power_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { - create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_power_0] if { $obj != "" } { } -# Create 'impl_1_route_report_route_status_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { - create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_route_status_0] if { $obj != "" } { } -# Create 'impl_1_route_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_timing_summary_0] if { $obj != "" } { set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj } -# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { - create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_incremental_reuse_0] if { $obj != "" } { } -# Create 'impl_1_route_report_clock_utilization_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { - create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_clock_utilization_0] if { $obj != "" } { } -# Create 'impl_1_route_report_bus_skew_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { - create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +# Create 'impl_1_copy_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_copy_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_route_report_bus_skew_0] if { $obj != "" } { set_property -name "options.warn_on_violation" -value "1" -objects $obj } -# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { - create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +# Create 'impl_1_copy_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_copy_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_timing_summary_0] if { $obj != "" } { set_property -name "options.max_paths" -value "10" -objects $obj set_property -name "options.report_unconstrained" -value "1" -objects $obj set_property -name "options.warn_on_violation" -value "1" -objects $obj } -# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) -if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { - create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +# Create 'impl_1_copy_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_copy_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1_copy_1 } -set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +set obj [get_report_configs -of_objects [get_runs impl_1_copy_1] impl_1_copy_1_post_route_phys_opt_report_bus_skew_0] if { $obj != "" } { set_property -name "options.warn_on_violation" -value "1" -objects $obj } -set obj [get_runs impl_1] -set_property -name "part" -value "xc7z020clg400-1" -objects $obj +set obj [get_runs impl_1_copy_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "part" -value "xc7z020clg400-2" -objects $obj +set_property -name "auto_rqs.directory" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/impl_1/impl_1_copy_1" -objects $obj +set_property -name "auto_incremental_checkpoint.directory" -value "$proj_dir/${_xil_proj_name_}.srcs/utils_1/imports/impl_1/impl_1_copy_1" -objects $obj set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj # set the current impl run -current_run -implementation [get_runs impl_1] +current_run -implementation [get_runs impl_1_copy_1] catch { if { $idrFlowPropertiesConstraints != {} } { set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints @@ -494,28 +554,24 @@ if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { create_dashboard_gadget -name {drc_1} -type drc } set obj [get_dashboard_gadgets [ list "drc_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj # Create 'methodology_1' gadget (if not found) if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { create_dashboard_gadget -name {methodology_1} -type methodology } set obj [get_dashboard_gadgets [ list "methodology_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj # Create 'power_1' gadget (if not found) if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { create_dashboard_gadget -name {power_1} -type power } set obj [get_dashboard_gadgets [ list "power_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj # Create 'timing_1' gadget (if not found) if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { create_dashboard_gadget -name {timing_1} -type timing } set obj [get_dashboard_gadgets [ list "timing_1" ] ] -set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj # Create 'utilization_1' gadget (if not found) if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { @@ -531,7 +587,6 @@ if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { create_dashboard_gadget -name {utilization_2} -type utilization } set obj [get_dashboard_gadgets [ list "utilization_2" ] ] -set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj move_dashboard_gadget -name {utilization_1} -row 0 -col 0 move_dashboard_gadget -name {power_1} -row 1 -col 0 diff --git a/top_src/constrains/top_module.xdc b/top_src/constrains/top_module.xdc new file mode 100644 index 0000000..1ce4b1b --- /dev/null +++ b/top_src/constrains/top_module.xdc @@ -0,0 +1,143 @@ +#开发板约束文件 - 优化版本 +# Fixed BUFR区域冲突问题 - 按Bank严格分组 + +# #时序约束 +# create_clock -period 20.000 -name sys_clk_50 [get_ports sys_clk_50] + +# #IO引脚约束 +# #----------------------系统时钟--------------------------- +# set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports sys_clk_50] +# # Bank34 MRCC + +#----------------------系统复位--------------------------- +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS25} [get_ports sys_rest_n] + +# ==================== A部分 - Bank34/35 分组 ==================== +#----------------------LVDS 时钟输入--------------------------- +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS_25} [get_ports CLK_A_p] +# Bank35 SRCC +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports CLK_A_n] +# Bank35 SRCC + +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[3]}] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[3]}] +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[2]}] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[2]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[1]}] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[1]}] +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[0]}] +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[0]}] +# 全部使用Bank35引脚保证同区域 + +#----------------------LVDS 输出通道0--------------------------- +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVDS_25} [get_ports CLK0_A_p] +# Bank35 MRCC +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25} [get_ports CLK0_A_n] +# Bank35 MRCC + +# 通道0数据端口 - 全部使用Bank35引脚 +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[3]}] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[3]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[2]}] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[2]}] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[1]}] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[1]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[0]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[0]}] + +#----------------------LVDS 输出通道1--------------------------- +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25} [get_ports CLK1_A_p] +# Bank35 MRCC +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVDS_25} [get_ports CLK1_A_n] +# Bank35 MRCC + +# 通道1数据端口 - 全部使用Bank35引脚 +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[3]}] +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[3]}] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[2]}] +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[2]}] +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[1]}] +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[1]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[0]}] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[0]}] + +#----------------------LVDS 输出通道2--------------------------- +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports CLK2_A_p] +# Bank35 SRCC +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports CLK2_A_n] +# Bank35 SRCC + +# 通道2数据端口 - 全部使用Bank34引脚（为其他通道释放Bank35资源） +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[3]}] +set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[3]}] +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[2]}] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[2]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[1]}] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[1]}] +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[0]}] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[0]}] +# 注意：通道2时钟在Bank35，数据在Bank34，需要BUFG跨区域 + +# ==================== B部分 - 严格Bank13分组 ==================== +#----------------------LVDS 时钟输入--------------------------- +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVDS_25} [get_ports CLK_B_p] +# Bank13 SRCC +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25} [get_ports CLK_B_n] +# Bank13 SRCC + +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[3]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[3]}] +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[2]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[2]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[1]}] +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[1]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[0]}] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[0]}] +# 全部使用Bank13引脚 + +#----------------------LVDS 输出通道0--------------------------- +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25} [get_ports CLK0_B_p] +# Bank13 MRCC +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25} [get_ports CLK0_B_n] +# Bank13 MRCC + +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[3]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[3]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[2]}] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[2]}] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[1]}] +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[1]}] +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[0]}] +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[0]}] +# 全部使用Bank13引脚 + +#----------------------LVDS 输出通道1--------------------------- +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports CLK1_B_p] +# Bank13 MRCC (从通道0调整而来) +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVDS_25} [get_ports CLK1_B_n] +# Bank13 MRCC + +# 通道1数据端口重新分配到Bank13可用引脚 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[3]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[3]}] +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[2]}] +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[2]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[1]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[1]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[0]}] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[0]}] +# 全部使用Bank13引脚 + +# ----------------------LVDS 输出通道2--------------------------- +#由于Bank13引脚资源有限，建议删除通道2或重新规划 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports CLK2_B_p] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports CLK2_B_n] + +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[3]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[3]}] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[2]}] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[2]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[1]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[1]}] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[0]}] diff --git a/top_src/rtl/top_module.v b/top_src/rtl/top_module.v new file mode 100644 index 0000000..a5de3e4 --- /dev/null +++ b/top_src/rtl/top_module.v @@ -0,0 +1,180 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2026/02/02 18:13:16 +// Design Name: +// Module Name: top_module +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top_module( + + input wire CLK_A_p,CLK_A_n, + input wire [3:0] DATA_A_p,DATA_A_n, + + input wire CLK_B_p,CLK_B_n, + input wire [3:0] DATA_B_p,DATA_B_n, + +// ------------------------------------------- + output wire CLK0_A_p,CLK0_A_n, + output wire [3:0] DATA0_A_p,DATA0_A_n, + + output wire CLK0_B_p,CLK0_B_n, + output wire [3:0] DATA0_B_p,DATA0_B_n, + +// ------------------------------------------- + output wire CLK1_A_p,CLK1_A_n, + output wire [3:0] DATA1_A_p,DATA1_A_n, + + output wire CLK1_B_p,CLK1_B_n, + output wire [3:0] DATA1_B_p,DATA1_B_n, + +// ------------------------------------------- + output wire CLK2_A_p,CLK2_A_n, + output wire [3:0] DATA2_A_p,DATA2_A_n, + + output wire CLK2_B_p,CLK2_B_n, + output wire [3:0] DATA2_B_p,DATA2_B_n, + + + input wire sys_clk_50, + input wire sys_rest_n + + + ); + + // lvds_1to3_copy_reg lvds_inst0( + // // 输入LVDS差分信号 + // .clk_in_p(CLK_A_p), + // .clk_in_n(CLK_A_n), + // .data_in_p(DATA_A_p), + // .data_in_n(DATA_A_n), + + // // 输出LVDS差分信号 + // .clk_out0_p(CLK0_A_p), + // .clk_out0_n(CLK0_A_n), + // .data_out0_p(DATA0_A_p), + // .data_out0_n(DATA0_A_n), + + // .clk_out1_p(CLK1_A_p), + // .clk_out1_n(CLK1_A_n), + // .data_out1_p(DATA1_A_p), + // .data_out1_n(DATA1_A_n), + + // .clk_out2_p(CLK2_A_p), + // .clk_out2_n(CLK2_A_n), + // .data_out2_p(DATA2_A_p), + // .data_out2_n(DATA2_A_n) + + // ); + + + lvds_1to3bypass lvds_1to3bypass_int0( + .CLK_p(CLK_A_p), + .CLK_n(CLK_A_n), + .DATA_p(DATA_A_p), + .DATA_n(DATA_A_n), + // ------------------------------------------- + .CLK0_p(CLK0_A_p), + .CLK0_n(CLK0_A_n), + .DATA0_p(DATA0_A_p), + .DATA0_n(DATA0_A_n), + // ------------------------------------------- + .CLK1_p(CLK1_A_p), + .CLK1_n(CLK1_A_n), + .DATA1_p(DATA1_A_p), + .DATA1_n(DATA1_A_n), + // ------------------------------------------- + .CLK2_p(CLK2_A_p), + .CLK2_n(CLK2_A_n), + .DATA2_p(DATA2_A_p), + .DATA2_n(DATA2_A_n), + // input sys_clk_50, + .io_reset(sys_rest_n) + ); + + + + wire [3:0] data_in_to_device; + wire clk_out; + + selectio_wiz_in lvds_in1( + // From the system into the device + .data_in_from_pins_p(DATA_B_p), // + .data_in_from_pins_n(DATA_B_n), // + + .data_in_to_device(data_in_to_device), + + .clk_in_p(CLK_B_p), // // Differential clock from IOB + .clk_in_n(CLK_B_n), // + + .clk_out(clk_out),// + + .io_reset(sys_rest_n) + + ); + + + selectio_wiz_out lvdsout0 ( + + // From the device out to the system + .data_out_from_device(data_in_to_device), + + .data_out_to_pins_p(DATA0_B_p), + .data_out_to_pins_n(DATA0_B_n), + .clk_to_pins_p(CLK0_B_p), + .clk_to_pins_n(CLK0_B_n), + + .clk_in(clk_out), // Fast clock input from PLL/MMCM + .clk_reset(sys_rest_n), + .io_reset(sys_rest_n) + ); + + selectio_wiz_out lvdsout1 ( + + // From the device out to the system + .data_out_from_device(data_in_to_device), + + .data_out_to_pins_p(DATA1_B_p), + .data_out_to_pins_n(DATA1_B_n), + .clk_to_pins_p(CLK1_B_p), + .clk_to_pins_n(CLK1_B_n), + + .clk_in(clk_out), // Fast clock input from PLL/MMCM + .clk_reset(sys_rest_n), + .io_reset(sys_rest_n) + ); + + selectio_wiz_out lvdsout2 ( + + // From the device out to the system + .data_out_from_device(data_in_to_device), + + .data_out_to_pins_p(DATA2_B_p), + .data_out_to_pins_n(DATA2_B_n), + .clk_to_pins_p(CLK2_B_p), + .clk_to_pins_n(CLK2_B_n), + + .clk_in(clk_out), // Fast clock input from PLL/MMCM + .clk_reset(sys_rest_n), + .io_reset(sys_rest_n) + ); + + +endmodule + + +