可以编译通过的工程

2026-02-05 18:42:08 +08:00
parent 2bd575c8ea
commit 68a9b7dceb
6 changed files with 1049 additions and 131 deletions
--- a/modules/LVDS/rtl/lvds_1to3bypass.v
+++ b/modules/LVDS/rtl/lvds_1to3bypass.v
@@ -0,0 +1,109 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2026/02/02 18:13:16
+// Design Name: 
+// Module Name: top_module
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module lvds_1to3bypass(
+
+    input wire          CLK_p,CLK_n,    
+    input wire [3:0]    DATA_p,DATA_n,    
+    //    -------------------------------------------
+    output wire         CLK0_p,CLK0_n,    
+    output wire [3:0]   DATA0_p,DATA0_n,    
+    //    -------------------------------------------
+    output wire         CLK1_p,CLK1_n,    
+    output wire [3:0]   DATA1_p,DATA1_n,
+    //    -------------------------------------------    
+    output wire         CLK2_p,CLK2_n,    
+    output wire [3:0]   DATA2_p,DATA2_n,   
+    // input sys_clk_50,    
+    input  io_reset 
+
+    );  
+    
+    
+    wire [3:0]  data_in_to_device;
+    wire        clk_out;
+    
+    selectio_wiz_in lvds_in1(
+      // From the system into the device
+      .data_in_from_pins_p(DATA_p), //
+      .data_in_from_pins_n(DATA_n),  //
+      
+      .data_in_to_device(data_in_to_device),
+      
+      .clk_in_p(CLK_p),  //    // Differential clock from IOB
+      .clk_in_n(CLK_n),  //
+      
+      .clk_out(clk_out),//      
+      .io_reset(io_reset)
+      
+    );
+    
+    
+    selectio_wiz_out lvdsout0 (    
+      // From the device out to the system
+      .data_out_from_device(data_in_to_device),
+      
+      .data_out_to_pins_p(DATA0_p),
+      .data_out_to_pins_n(DATA0_n),
+      .clk_to_pins_p(CLK0_p),
+      .clk_to_pins_n(CLK0_n),
+      
+      .clk_in(clk_out),        // Fast clock input from PLL/MMCM
+      .clk_reset(io_reset),
+      .io_reset(io_reset)    
+    );
+    
+    selectio_wiz_out lvdsout1 (
+    
+      // From the device out to the system
+      .data_out_from_device(data_in_to_device),
+      
+      .data_out_to_pins_p(DATA1_p),
+      .data_out_to_pins_n(DATA1_n),
+      .clk_to_pins_p(CLK1_p),
+      .clk_to_pins_n(CLK1_n),
+      
+      .clk_in(clk_out),        // Fast clock input from PLL/MMCM
+      .clk_reset(io_reset),
+      .io_reset(io_reset)    
+    );
+        
+    selectio_wiz_out lvdsout2 (
+    
+      // From the device out to the system
+      .data_out_from_device(data_in_to_device),
+      
+      .data_out_to_pins_p(DATA2_p),
+      .data_out_to_pins_n(DATA2_n),
+      .clk_to_pins_p(CLK2_p),
+      .clk_to_pins_n(CLK2_n),
+      
+      .clk_in(clk_out),        // Fast clock input from PLL/MMCM
+      .clk_reset(io_reset),
+      .io_reset(io_reset)    
+    );
+    
+    
+endmodule
+
+
+