可以编译通过的工程

top_src/constrains/top_module.xdc

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+#开发板约束文件 - 优化版本
+# Fixed BUFR区域冲突问题 - 按Bank严格分组
+
+# #时序约束
+# create_clock -period 20.000 -name sys_clk_50 [get_ports sys_clk_50] 
+
+# #IO引脚约束
+# #----------------------系统时钟---------------------------
+# set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports sys_clk_50]   
+# # Bank34 MRCC
+
+#----------------------系统复位---------------------------
+set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS25} [get_ports sys_rest_n]
+
+# ==================== A部分 - Bank34/35 分组 ====================
+#----------------------LVDS 时钟输入---------------------------
+set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS_25} [get_ports CLK_A_p]      
+# Bank35 SRCC
+set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports CLK_A_n]      
+# Bank35 SRCC
+
+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[3]}]
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[3]}]
+set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[2]}]
+set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[2]}]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[1]}]
+set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[1]}]
+set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVDS_25} [get_ports {DATA_A_p[0]}]
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25} [get_ports {DATA_A_n[0]}]
+# 全部使用Bank35引脚保证同区域
+
+#----------------------LVDS 输出通道0---------------------------
+set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVDS_25} [get_ports CLK0_A_p]    
+# Bank35 MRCC
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25} [get_ports CLK0_A_n]    
+# Bank35 MRCC
+
+# 通道0数据端口 - 全部使用Bank35引脚
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[3]}]
+set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[3]}]
+set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[2]}]
+set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[2]}]
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[1]}]
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[1]}]
+set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports {DATA0_A_p[0]}]
+set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVDS_25} [get_ports {DATA0_A_n[0]}]
+
+#----------------------LVDS 输出通道1---------------------------
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25} [get_ports CLK1_A_p]    
+# Bank35 MRCC
+set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVDS_25} [get_ports CLK1_A_n]    
+# Bank35 MRCC
+
+# 通道1数据端口 - 全部使用Bank35引脚
+set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[3]}]
+set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[3]}]
+set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[2]}]
+set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[2]}]
+set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[1]}]
+set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[1]}]
+set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports {DATA1_A_p[0]}]
+set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS_25} [get_ports {DATA1_A_n[0]}]
+
+#----------------------LVDS 输出通道2---------------------------
+set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports CLK2_A_p]    
+# Bank35 SRCC
+set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports CLK2_A_n]    
+# Bank35 SRCC
+
+# 通道2数据端口 - 全部使用Bank34引脚（为其他通道释放Bank35资源）
+set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[3]}]
+set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[3]}]
+set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[2]}]
+set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[2]}]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[1]}]
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[1]}]
+set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVDS_25} [get_ports {DATA2_A_p[0]}]
+set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS_25} [get_ports {DATA2_A_n[0]}]
+# 注意：通道2时钟在Bank35，数据在Bank34，需要BUFG跨区域
+
+# ==================== B部分 - 严格Bank13分组 ====================
+#----------------------LVDS 时钟输入---------------------------
+set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVDS_25} [get_ports CLK_B_p]     
+# Bank13 SRCC
+set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25} [get_ports CLK_B_n]     
+# Bank13 SRCC
+
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[3]}]
+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[3]}]
+set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[2]}]
+set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[2]}]
+set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[1]}]
+set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[1]}]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVDS_25} [get_ports {DATA_B_p[0]}]
+set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25} [get_ports {DATA_B_n[0]}]
+# 全部使用Bank13引脚
+
+#----------------------LVDS 输出通道0---------------------------
+set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVDS_25} [get_ports CLK0_B_p]      
+# Bank13 MRCC
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVDS_25} [get_ports CLK0_B_n]     
+# Bank13 MRCC
+
+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[3]}]
+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[3]}]
+set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[2]}]
+set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[2]}]
+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[1]}]
+set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[1]}]
+set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_p[0]}]
+set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports {DATA0_B_n[0]}]
+# 全部使用Bank13引脚
+
+#----------------------LVDS 输出通道1---------------------------
+set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports CLK1_B_p]      
+# Bank13 MRCC (从通道0调整而来)
+set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVDS_25} [get_ports CLK1_B_n]      
+# Bank13 MRCC
+
+# 通道1数据端口重新分配到Bank13可用引脚
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[3]}]
+set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[3]}]
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[2]}]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[2]}]
+set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[1]}]
+set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[1]}]
+set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_p[0]}]
+set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVDS_25} [get_ports {DATA1_B_n[0]}]
+# 全部使用Bank13引脚
+
+# ----------------------LVDS 输出通道2---------------------------
+#由于Bank13引脚资源有限，建议删除通道2或重新规划
+set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports CLK2_B_p]     
+set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports CLK2_B_n]     
+
+set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[3]}]
+set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[3]}]
+set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[2]}]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[2]}]
+set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[1]}]
+set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[1]}]
+set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25} [get_ports {DATA2_B_p[0]}]
+set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVDS_25} [get_ports {DATA2_B_n[0]}]