`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 2026/01/25 21:01:38 // Design Name: // Module Name: lvds_1to3_copy_reg // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module lvds_1to3_copy_reg ( // 输入LVDS差分信号 input wire clk_in_p, clk_in_n, input wire [2:0] data_in_p, data_in_n, // 输出LVDS差分信号 output wire clk_out0_p, clk_out0_n, output wire clk_out1_p, clk_out1_n, output wire clk_out2_p, clk_out2_n, output wire [2:0] data_out0_p, data_out0_n, output wire [2:0] data_out1_p, data_out1_n, output wire [2:0] data_out2_p, data_out2_n ); // 输入缓冲 wire clk_ibuf; wire [2:0] data_ibuf; IBUFDS clk_ibuf_inst (.O(clk_ibuf), .I(clk_in_p), .IB(clk_in_n)); generate for (genvar i = 0; i < 3; i = i + 1) begin IBUFDS data_ibuf_inst (.O(data_ibuf[i]), .I(data_in_p[i]), .IB(data_in_n[i])); end endgenerate // 全局时钟 wire clk_bufg; BUFG bufg_inst (.I(clk_ibuf), .O(clk_bufg)); // 寄存器同步 reg [2:0] data_sync0, data_sync1, data_sync2; always @(posedge clk_bufg) begin data_sync0 <= data_ibuf; data_sync1 <= data_ibuf; data_sync2 <= data_ibuf; end // 输出缓冲 generate for (genvar i = 0; i < 3; i = i + 1) begin OBUFDS data_obuf0_inst (.O(data_out0_p[i]), .OB(data_out0_n[i]), .I(data_sync0[i])); OBUFDS data_obuf1_inst (.O(data_out1_p[i]), .OB(data_out1_n[i]), .I(data_sync1[i])); OBUFDS data_obuf2_inst (.O(data_out2_p[i]), .OB(data_out2_n[i]), .I(data_sync2[i])); end endgenerate // 时钟输出缓冲 OBUFDS clk_obuf0_inst (.O(clk_out0_p), .OB(clk_out0_n), .I(clk_bufg)); OBUFDS clk_obuf1_inst (.O(clk_out1_p), .OB(clk_out1_n), .I(clk_bufg)); OBUFDS clk_obuf2_inst (.O(clk_out2_p), .OB(clk_out2_n), .I(clk_bufg)); endmodule