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panxiang 2bd575c8ea 初始的工程参考
2026-02-02 17:58:25 +08:00
modules/LVDS
初始的工程参考
2026-02-02 17:58:25 +08:00
.gitignore
初始的工程参考
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project_gen.tcl
初始的工程参考
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README.md
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Sourceprj.bat
初始的工程参考
2026-02-02 17:58:25 +08:00

README.md

LVDS1M

LVDS 1 对 多 输出

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Description
LVDS1M
Readme 46 KiB
Languages
Tcl 69.4%
Verilog 27.9%
Batchfile 2.7%