76 lines
2.1 KiB
Verilog
76 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/01/25 21:01:38
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// Design Name:
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// Module Name: lvds_1to3_copy_reg
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module lvds_1to3_copy_reg (
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// 输入LVDS差分信号
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input wire clk_in_p, clk_in_n,
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input wire [2:0] data_in_p, data_in_n,
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// 输出LVDS差分信号
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output wire clk_out0_p, clk_out0_n,
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output wire clk_out1_p, clk_out1_n,
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output wire clk_out2_p, clk_out2_n,
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output wire [2:0] data_out0_p, data_out0_n,
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output wire [2:0] data_out1_p, data_out1_n,
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output wire [2:0] data_out2_p, data_out2_n
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);
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// 输入缓冲
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wire clk_ibuf;
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wire [2:0] data_ibuf;
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IBUFDS clk_ibuf_inst (.O(clk_ibuf), .I(clk_in_p), .IB(clk_in_n));
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generate
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for (genvar i = 0; i < 3; i = i + 1) begin
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IBUFDS data_ibuf_inst (.O(data_ibuf[i]), .I(data_in_p[i]), .IB(data_in_n[i]));
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end
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endgenerate
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// 全局时钟
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wire clk_bufg;
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BUFG bufg_inst (.I(clk_ibuf), .O(clk_bufg));
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// 寄存器同步
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reg [2:0] data_sync0, data_sync1, data_sync2;
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always @(posedge clk_bufg) begin
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data_sync0 <= data_ibuf;
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data_sync1 <= data_ibuf;
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data_sync2 <= data_ibuf;
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end
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// 输出缓冲
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generate
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for (genvar i = 0; i < 3; i = i + 1) begin
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OBUFDS data_obuf0_inst (.O(data_out0_p[i]), .OB(data_out0_n[i]), .I(data_sync0[i]));
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OBUFDS data_obuf1_inst (.O(data_out1_p[i]), .OB(data_out1_n[i]), .I(data_sync1[i]));
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OBUFDS data_obuf2_inst (.O(data_out2_p[i]), .OB(data_out2_n[i]), .I(data_sync2[i]));
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end
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endgenerate
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// 时钟输出缓冲
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OBUFDS clk_obuf0_inst (.O(clk_out0_p), .OB(clk_out0_n), .I(clk_bufg));
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OBUFDS clk_obuf1_inst (.O(clk_out1_p), .OB(clk_out1_n), .I(clk_bufg));
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OBUFDS clk_obuf2_inst (.O(clk_out2_p), .OB(clk_out2_n), .I(clk_bufg));
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endmodule
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