110 lines
2.7 KiB
Verilog
110 lines
2.7 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/02/02 18:13:16
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// Design Name:
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// Module Name: top_module
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module lvds_1to3bypass(
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input wire CLK_p,CLK_n,
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input wire [3:0] DATA_p,DATA_n,
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// -------------------------------------------
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output wire CLK0_p,CLK0_n,
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output wire [3:0] DATA0_p,DATA0_n,
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// -------------------------------------------
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output wire CLK1_p,CLK1_n,
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output wire [3:0] DATA1_p,DATA1_n,
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// -------------------------------------------
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output wire CLK2_p,CLK2_n,
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output wire [3:0] DATA2_p,DATA2_n,
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// input sys_clk_50,
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input io_reset
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);
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wire [3:0] data_in_to_device;
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wire clk_out;
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selectio_wiz_in lvds_in1(
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// From the system into the device
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.data_in_from_pins_p(DATA_p), //
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.data_in_from_pins_n(DATA_n), //
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.data_in_to_device(data_in_to_device),
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.clk_in_p(CLK_p), // // Differential clock from IOB
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.clk_in_n(CLK_n), //
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.clk_out(clk_out),//
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.io_reset(io_reset)
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);
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selectio_wiz_out lvdsout0 (
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// From the device out to the system
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.data_out_from_device(data_in_to_device),
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.data_out_to_pins_p(DATA0_p),
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.data_out_to_pins_n(DATA0_n),
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.clk_to_pins_p(CLK0_p),
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.clk_to_pins_n(CLK0_n),
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.clk_in(clk_out), // Fast clock input from PLL/MMCM
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.clk_reset(io_reset),
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.io_reset(io_reset)
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);
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selectio_wiz_out lvdsout1 (
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// From the device out to the system
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.data_out_from_device(data_in_to_device),
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.data_out_to_pins_p(DATA1_p),
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.data_out_to_pins_n(DATA1_n),
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.clk_to_pins_p(CLK1_p),
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.clk_to_pins_n(CLK1_n),
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.clk_in(clk_out), // Fast clock input from PLL/MMCM
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.clk_reset(io_reset),
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.io_reset(io_reset)
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);
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selectio_wiz_out lvdsout2 (
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// From the device out to the system
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.data_out_from_device(data_in_to_device),
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.data_out_to_pins_p(DATA2_p),
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.data_out_to_pins_n(DATA2_n),
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.clk_to_pins_p(CLK2_p),
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.clk_to_pins_n(CLK2_n),
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.clk_in(clk_out), // Fast clock input from PLL/MMCM
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.clk_reset(io_reset),
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.io_reset(io_reset)
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);
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endmodule
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