181 lines
4.6 KiB
Verilog
181 lines
4.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2026/02/02 18:13:16
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// Design Name:
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// Module Name: top_module
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module top_module(
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input wire CLK_A_p,CLK_A_n,
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input wire [3:0] DATA_A_p,DATA_A_n,
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input wire CLK_B_p,CLK_B_n,
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input wire [3:0] DATA_B_p,DATA_B_n,
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// -------------------------------------------
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output wire CLK0_A_p,CLK0_A_n,
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output wire [3:0] DATA0_A_p,DATA0_A_n,
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output wire CLK0_B_p,CLK0_B_n,
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output wire [3:0] DATA0_B_p,DATA0_B_n,
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// -------------------------------------------
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output wire CLK1_A_p,CLK1_A_n,
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output wire [3:0] DATA1_A_p,DATA1_A_n,
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output wire CLK1_B_p,CLK1_B_n,
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output wire [3:0] DATA1_B_p,DATA1_B_n,
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// -------------------------------------------
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output wire CLK2_A_p,CLK2_A_n,
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output wire [3:0] DATA2_A_p,DATA2_A_n,
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output wire CLK2_B_p,CLK2_B_n,
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output wire [3:0] DATA2_B_p,DATA2_B_n,
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input wire sys_clk_50,
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input wire sys_rest_n
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);
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// lvds_1to3_copy_reg lvds_inst0(
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// // 输入LVDS差分信号
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// .clk_in_p(CLK_A_p),
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// .clk_in_n(CLK_A_n),
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// .data_in_p(DATA_A_p),
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// .data_in_n(DATA_A_n),
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// // 输出LVDS差分信号
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// .clk_out0_p(CLK0_A_p),
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// .clk_out0_n(CLK0_A_n),
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// .data_out0_p(DATA0_A_p),
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// .data_out0_n(DATA0_A_n),
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// .clk_out1_p(CLK1_A_p),
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// .clk_out1_n(CLK1_A_n),
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// .data_out1_p(DATA1_A_p),
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// .data_out1_n(DATA1_A_n),
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// .clk_out2_p(CLK2_A_p),
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// .clk_out2_n(CLK2_A_n),
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// .data_out2_p(DATA2_A_p),
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// .data_out2_n(DATA2_A_n)
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// );
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lvds_1to3bypass lvds_1to3bypass_int0(
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.CLK_p(CLK_A_p),
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.CLK_n(CLK_A_n),
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.DATA_p(DATA_A_p),
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.DATA_n(DATA_A_n),
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// -------------------------------------------
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.CLK0_p(CLK0_A_p),
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.CLK0_n(CLK0_A_n),
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.DATA0_p(DATA0_A_p),
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.DATA0_n(DATA0_A_n),
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// -------------------------------------------
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.CLK1_p(CLK1_A_p),
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.CLK1_n(CLK1_A_n),
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.DATA1_p(DATA1_A_p),
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.DATA1_n(DATA1_A_n),
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// -------------------------------------------
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.CLK2_p(CLK2_A_p),
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.CLK2_n(CLK2_A_n),
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.DATA2_p(DATA2_A_p),
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.DATA2_n(DATA2_A_n),
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// input sys_clk_50,
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.io_reset(sys_rest_n)
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);
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wire [3:0] data_in_to_device;
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wire clk_out;
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selectio_wiz_in lvds_in1(
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// From the system into the device
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.data_in_from_pins_p(DATA_B_p), //
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.data_in_from_pins_n(DATA_B_n), //
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.data_in_to_device(data_in_to_device),
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.clk_in_p(CLK_B_p), // // Differential clock from IOB
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.clk_in_n(CLK_B_n), //
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.clk_out(clk_out),//
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.io_reset(sys_rest_n)
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);
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selectio_wiz_out lvdsout0 (
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// From the device out to the system
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.data_out_from_device(data_in_to_device),
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.data_out_to_pins_p(DATA0_B_p),
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.data_out_to_pins_n(DATA0_B_n),
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.clk_to_pins_p(CLK0_B_p),
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.clk_to_pins_n(CLK0_B_n),
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.clk_in(clk_out), // Fast clock input from PLL/MMCM
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.clk_reset(sys_rest_n),
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.io_reset(sys_rest_n)
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);
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selectio_wiz_out lvdsout1 (
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// From the device out to the system
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.data_out_from_device(data_in_to_device),
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.data_out_to_pins_p(DATA1_B_p),
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.data_out_to_pins_n(DATA1_B_n),
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.clk_to_pins_p(CLK1_B_p),
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.clk_to_pins_n(CLK1_B_n),
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.clk_in(clk_out), // Fast clock input from PLL/MMCM
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.clk_reset(sys_rest_n),
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.io_reset(sys_rest_n)
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);
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selectio_wiz_out lvdsout2 (
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// From the device out to the system
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.data_out_from_device(data_in_to_device),
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.data_out_to_pins_p(DATA2_B_p),
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.data_out_to_pins_n(DATA2_B_n),
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.clk_to_pins_p(CLK2_B_p),
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.clk_to_pins_n(CLK2_B_n),
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.clk_in(clk_out), // Fast clock input from PLL/MMCM
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.clk_reset(sys_rest_n),
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.io_reset(sys_rest_n)
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);
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endmodule
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